- In I2C only two bi-directional lines Serial
Data (SDA) & Serial Clock (SCL) are required to carry
information between the devices connected to the bus.
- Each I2C device is recognized by a unique 7-bit address. The
device that initiates the communication is called MASTER.
- The master controls the clock signal. Whereas the device
being addressed by the Master is called as SLAVE.
- Generation of clock signals on the I2C-bus is always the
responsibility of master devices; each master generates its own
clock signals when transferring data on the bus.
Data on the I2C bus can be transferred in three modes:
1) Standard Mode: 100kbps.
2) Fast Mode: 400kbps
3) High Speed Mode: 3.4Mbps.The maximum number of nodes is obviously limited by the address space, and also by the total bus capacitance of 400 pf.
- The master begins the communication by issuing the
followed by 7- bit unique address/Control Byte of the device it
wants to access.
- The eighth bit after the start specifies if the
slave is now to receive (0) or to transmit (1).
- After reciving the address all IC's on the I2C bus will
compare with their own address & if the address does not match,
it will wait till a STOP is received.
- If address matches a ACKNOWLEDGE
signal is generated by the Slave.
- Following receipt of the slave’s address acknowledgment,
the master continues with the data transfer. If a write operationhas
been ordered, the master transmits the remaining data, with the
slave acknowledging receipt of each byte.
- If the master has ordered a read operation, it releases the
data line and clocks in data sent by the slave. After each byte is
received, the master generates an acknowledge condition on the bus.
- The acknowledge is omitted following receipt of the last
byte. The master terminates all operations by generating a stop
condition on the bus. The master may also abort a data transfer at
any time by generating a stop condition.
1.BUS NOT BUSY:
BOTH Data & Clock lines remain high.
A HIGH to LOW transition of SDA line while the SCL is high.
A LOW to HIGH transition of SDA line while the SCL is high.
4.DATA VALID:During Data transfer, the data on must be changed during the LOW period of the clock signal i.e. the data line must remain stable whenever the clock line is HIGH. Any change in data line while clock is HIGH will be interpreted as START or STOP condition.
Each device when addressed to has to generate an acknowledge signal after the reception of each byte. The master generated an extra clock pulse which is associated with the ACKNOWLEDGE bit. The device that acknowledges pulls down the SDA line during the acknowledge clock pulse.
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